Integrated circuit with signature computation

ABSTRACT

The present invention relates to an integrated circuit (DEC V) for processing a plurality of data samples (P) of a data signal (I), wherein said integrated circuit is associated with a counter (CT) and comprises means (SIGN M) for computing a signature, said counter (CT) being adapted to trigger and stop a computation of a signature of said data signal (I), said signature being recalculated each time a data sample (P) of said data signal is output by said integrated circuit (DEC V). Use: Video decoder in a set-top-box.

FIELD OF THE INVENTION

The present invention relates to an integrated circuit for processing aplurality of data samples of a data signal and to a corresponding testmethod.

Such integrated circuit may be used in, for example, a computer.

BACKGROUND OF THE INVENTION

An integrated circuit in a computer is used for displaying some datasignals such as images on the screen of said computer for example, saiddata signals comprising data samples that are pixels in this case. Animage usually comprises 1280*1024 pixels and a pixel is usually definedby thirty-two bits. This leads to about forty million bits to betransferred onto the screen for an image. To avoid transferring so manydata, a solution is proposed and described in the U.S. Pat. No.5,862,150 referenced “Video Frame Signature Capture”.

It consists in using a random access memory digital to analog converteralso called RAMDAC that comprises a signature generator, a centralprocessing unit CPU and a digital bus. The computer comprises a framebuffer that contains an image to be displayed on the screen. The RAMDACpermits to compute a signature on the image that is the frame buffer andto compare the result to a “good signature” and this by means of thesignature generator, the central processing unit CPU and the digitalbus.

One drawback of such solution is that it does not test the images inreal time. Indeed, the RAMDAC takes the pixels from the frame buffer,which describes a fixed image to be displayed on the screen of thecomputer. Thus, when the images displayed on the screen of the computerare images of a video film for example, one does not test the integratedcircuit in its functional environment, i.e. the images of a video filmas soon as they are displayed on the screen of the computer. Moreover, acentral processing unit CPU is needed to compute the signature and thissolution is only specific to a RAMDAC. The central processing unit CPUleads to a high consumption and to the use of software.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the invention to provide an integratedcircuit for processing a plurality of data samples of a data signal anda corresponding test method, which allow testing data signals in realtime without using a central processing unit CPU.

To this end, there is provided an integrated circuit for processing aplurality of data samples of a data signal, wherein said integratedcircuit is associated to a counter and comprises means for computing asignature, said counter being adapted to trigger and stop a computationof a signature of said data signal, said signature being recalculatedeach time a data sample of said data signal is output by said integratedcircuit.

In addition, there is provided a method for testing an integratedcircuit for processing a plurality of data samples of a data signal,said integrated circuit being associated to a counter, wherein saidmethod comprises the steps of:

-   -   inserting said integrated circuit in a data testing system,    -   computing a signature for all the data signals generated by said        integrated circuit by means of said counter which is adapted to        trigger and stop a computation of a signature of a signal, said        signature being recalculated each time a data sample of a data        signal is output by said integrated circuit, and    -   comparing in real time said computed signatures with some        registered signatures of a referenced integrated circuit each        time a signature is computed.

As we will see in detail further on, as the signature is recalculatedeach time a data sample of a data signal is output by the integratedcircuit by means of said counter, it permits to test the integratedcircuit in real time and by means of the counter without any centralprocessing unit.

Advantageously, in a non-limited embodiment, the counter is based on aninternal clock within the internal circuit and on a verticalsynchronization signal of said data signal, said internal clock definingthe sequencing of a signature computation and said verticalsynchronization signal defining the end of each signature computation.

Preferably, in a non-limited embodiment, the integrated circuitcomprises at least a digital to analog converter that comprises saidinternal clock, the data samples of a data signal being output by saidintegrated circuit at each clock cycle of said internal clock.

Preferably, in a non-limited embodiment, a data signal comprises anactive zone and an inactive zone, which are both taken into account forthe signature computation.

Advantageously, in a non-limited embodiment, the integrated circuitfurther comprises:

-   -   an initialization input for outputting a signal defining that        said integrated circuit is in a test mode or not,    -   a clock pin for receiving a clock signal of a data testing        system,    -   a flag for enabling the reading of a signature by a data testing        system, and    -   a serial output for outputting the bits of a signature to said        data testing system.

Preferably, in a non-limited embodiment, the integrated circuit furthercomprises a second output for outputting said vertical synchronizationsignal to a data testing system.

Advantageously, in a non-limited embodiment, the integrated circuitfurther comprises activation/deactivation means for defining a timewindow during which a comparison of a signature computed by saidcomputation means with a referenced signature can be performed.

Preferably, in a non-limited embodiment, the integrated circuit furthercomprises a delay line for initializing the signature computation block.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects, features and advantages of the invention will becomeapparent upon reading the following detailed description and uponreference to the accompanying drawings in which:

FIG. 1 illustrates an integrated circuit and a counter according to theinvention,

FIG. 2 is a data signal generated by a video processing system to saidintegrated circuit of FIG. 1,

FIG. 3 illustrated in more detail the integrated circuit of FIG. 1,

FIG. 4 is a diagram showing a scheduling of a signature computation bymeans of the counter of FIG. 1, and

FIG. 5 illustrates a schematic diagram of signature computation meanswithin the integrated circuit of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, functions or constructions well known tothe person skilled in the art are not described in detail since theywould obscure the invention in unnecessary detail.

The present invention relates to an integrated circuit for processing aplurality of data samples of a data signal.

An example in a video application is taken for the further description.Of course, it does not exclude other examples in other applications suchas computer.

Such an integrated circuit can be found in a video processing deviceVCS, which is described in FIG. 1. Said video processing system VCScomprises a channel satellite decoder DEC_V for decoding said MPEGsignal representing a video film VIDEO, said decoder being theintegrated circuit and said video film comprising data signals such asimages I with data samples such as pixels.

In the application given by way of example, a set-top-box is taken as anexample for such a video processing device, the example being notrestricted to such a set-top-box or such a decoder.

Generally a set-top-box comprises also a tuner TUNE for receiving adigital signal DIG_S from a parabola, said tuner being adapted todemodulate said digital signal and to output an MPEG signal MPEG_S. Suchset-top-box is generally associated with a television TV with a screenon which images I of the video film VIDEO are displayed.

Note that there are two main image formats, a European one calledPAL/SECAM and a United States one called NTSC defining 50 images/sec or60 images/sec, respectively.

An image I of a video film is illustrated in FIG. 2. Such an image Icomprises a plurality of pixels P. It usually comprises lines L0 to LNof pixels P. A horizontal synchronization signal HS and a verticalsynchronization signal VS are used to define the beginning of a line inan image I and the beginning of an image I respectively as well-known tothose skilled in the art, one image comprising an active zone Z1 and aninactive zone Z2. The images of a video film and thus the pixels of saidimages are generated by the channel satellite decoder DEC_V.

An integrated circuit such as a channel satellite decoder DEC_V isdescribed in FIG. 3. It comprises a central processing unit CPU1 fordecoding the input MPEG signal and for generating the images formingsaid video film. It also comprises 6 digital to analog converters DACfor the R G B, Y C and CVBS video formats, well known to those skilledin the art, each digital to analog converter DAC comprising an internalclock CLK and a data bus.

Regarding the different video formats, the CVBS format corresponds to animage that can be registered on a recorder, whereas the RGB formatcorresponds to an image that can be displayed on the TV screen and theYC format corresponds to an image for the home video for example.

In order to test the channel satellite decoder DEC_V in its functionalenvironment, a signature of each image of a video film is computed andthen compared afterwards to a reference signature of each image.Preferably, the signature is a CRC also called cyclic redundancychecksum well known to those skilled in the art.

The signature of an image I is processed as follows.

When a first pixel of an image I is output by a digital to analogconverter DAC, for example the first digital to analog converter DAC1corresponding to the R format, the computation of the signature of saidimage I is triggered. The triggering is performed by an associatedcounter CT. Preferably, in a non-limited embodiment, the integratedcircuit DEC_V comprises said counter CT and said counter CT is based onthe internal clock CLK1 of said digital to analog converter DAC1 and onthe vertical synchronization signal VS of the image I. Said internalclock CLK1 defines the sequencing of a signature computation and saidvertical synchronization signal VS defines the beginning and the end ofsaid signature computation.

Note that the vertical synchronization signal VS corresponds to the sizeof the TV screen, i.e. is of 720*576 lines, and lasts 20 ms for thePAL/SECAM format. At each rising edge of a VS, the signature of theimage I is triggered. Then at each clock cycle of the internal clockCLK1, the signature is recalculated, a pixel being output at each clockcycle of the digital to analog converter DAC1. Note that a pixel is adigital value corresponding to an analog signal that is output by adigital to analog converter DAC. Practically, in the example taken, itmeans that the signature is recalculated each time a pixel of said imageI is displayed on the TV screen.

Then at the end of the 20 ms, the signature of said image I is stopped.

When another signal VS arrives, that is to say, another image I is to beprocessed by the digital to analog converter DAC1, the signature of thissecond image is computed. And so on for all the images I of a video filmVIDEO.

Note that this signature computation is performed in parallel for allthe 6 digital to analog converters DAC, and that preferably 10 bits areallocated for each signature corresponding to a digital to analogconverter DAC resulting in 60 bits for the whole signatures. Hence,these 60 bits will be used to know if the decoder DEC_V is in order orfaulty as described below, instead of the whole image I of usually 1Mbytes.

The signature computation as described before is used to test thechannel satellite decoder DEC_V in its functional environment asfollows.

There is a data testing system also called testing board AFTE on whichan integrated circuit such as the decoder to be tested is placed. Thetesting board comprises a central processing unit CPU2 and a clock CLK2(not represented) that runs at 10 MHz.

In order to test an integrated circuit, the following steps areperformed.

But before the testing, a learning step is performed as follows. Areference integrated circuit DEC_RF also called golden device isinserted in the testing board AFTE, signatures for all the images of thevideo film generated by said integrated circuit DEC_RF are computed andregistered in a memory, preferably a read only memory ROM associatedwith said testing board AFTE. The integrated circuit DEC_V is put in atest mode by the testing board via a controller of said testing board.

Then the testing is performed. The integrated circuit DEC_V to be testedis inserted in the testing board AFTE and signatures for all the imagesof the video film generated by said integrated circuit by means of saidcounter CT are computed. Note that for the purpose of the testing, theMPEG signal MPEG_S usually generated by the set-top-box is generatedhere by the testing board AFTE itself.

To this end, as illustrated in FIG. 3, the integrated circuit DEC_Vfurther comprises:

-   -   a signature computation block SIGN_M comprising flips flops and        memory to store the signatures (flips flops and memory not        represented),    -   an initialization input ENABL adapted to output a signal        defining that the integrated circuit is in a testing mode or        not, and which is connected to the signature computation block        SIGN_M,    -   a first clock pin CL adapted to receive a signal of a sample        clock VCP that defines the frequency of the pixels of an image        I,    -   a second clock pin TCK adapted to receive a signal of a clock        CLK2 of the testing board AFTE, which is connected to said        testing board,    -   a flag TDI, which is a pin connected to the signature        computation block SIGN_M and to the testing board, adapted to        enable the reading of a signature by said testing board,    -   a serial output TDO adapted to output the bits of a signature to        the testing board AFTE, said serial output using a first        multiplexer MUX1 and being connected to the testing board,    -   a second output TVS adapted to output the vertical        synchronization signal VS to the testing board AFTE, said second        output using a second multiplexer MUX2 and being connected to        the testing board,    -   a delay line comprising four registers also called flip flops        FF1 to FF4 and a logic AND gate, said flip flops being connected        to the second clock input TCK and to the signature computation        block SIGN_M and running at the frequency of the sample clock        VCP, and    -   an initialization pin INIT adapted to receive a signal coming        from the delay line.

Note that the integrated circuit DEC_V comprises a bus JTAG that isdescribed in a standard referenced IEEE 1149.1. This bus comprises thethree pins TDI, TDO and TCK.

Hence, in order to test the integrated circuit DEC_V, one uses somestandard pins. It avoids adding more pins to such an integrated circuitDEC_V.

Note that in the example of video taken, the sample frequency VCP of thepixels of an image I is 27 MHz for the standard CCIR 6.5.6 of videotransmission for example.

Note that the four pins the TCK, TDI, TDO, TVS used already exist onusual integrated circuit. Only their functionality is changed accordingto the test mode. Indeed, for example, in the usual mode that is to saywhen the integrated circuit is in its functional environment, the TVSpin outputs another signal GPIO known as general purpose IO instead ofthe VS signal, and the serial output TDO outputs a usual test dataoutput signal.

Hence, no extra pins are added for the testing of an integrated circuitsuch as a decoder. Note that the function of the multiplexers MUX1 andMUX2 is to output the right signal on the corresponding pins TDO, TVSdepending on the test mode or usually on the integrated circuit.

When the decoder DEC_V begins to generate a first image I, the signaturecomputation and the comparison in real time can begin. Thesecomputations and comparisons last during a time window that iscontrolled by the decoder DEC_V itself. In order to activate thecomparisons window, the decoder DEC_V sends a first window signal WS tothe testing board AFTE via an interrupt pin PIOX. Then, when the lastimage I is generated, the decoder DEC_V sends a second window signal todeactivate the comparisons window. The time called comparison timewindow between the first window signal WS and the second one can last 10sec for example.

During such a comparisons window, when a signature has been computed asdescribed above for an image I, that is to say each 20 ms, theintegrated circuit DEC_V outputs a vertical synchronization signal VSassociated with the image I processed on the second output TVS. Thisvertical synchronization signal VS is on its rising edge as illustratedin the FIG. 4. At each rising edge, the computed signatures are storedin the flips flops by the signature computation block SIGN_M and twoclock cycles of TCK later, the flip flops of the signature computationblock SIGN_M are reinitialized. Preferably, 60 flip flops are used tostore the 60 bits of the 6 computed signatures corresponding to the 6digital to analog converters DAC. Hence, the 6 CRC are computed inparallel.

Note that the delay of the 2 clock cycles TCK is obtained by means ofthe delay line with the four flip-flops FF1 to FF4. Thus, the delay linepermits to initialize the signature computation block SIGN_M correctly,i.e. the computation signatures.

Then the testing board AFTE enables the reading of the computedsignature by means of the flag TDI. This flag is set to 1. Note thatthis enabling is performed whenever wanted by the testing board, within20 ms, i.e. within two rising edges of the vertical synchronizationsignal VS.

When the flag TDI is enabled, the testing board AFTE sends 60 clockcycles on the second clock pin TCK to read the computed signaturescorresponding to the 6 digital to analog converters DAC on the serialoutput TDO, 10 bits being used for one signature. At the serial output,the testing board AFTE catches the 60 bits of the signatures.

Note that in the example of the FIG. 4, the CRC0 represents the 6 CRCconcatenated corresponding to the 6 digital to analog converters DAC ofa first image I0. The CRC1 represents the 6 CRC concatenatedcorresponding to the 6 is digital to analog converters DAC of a secondimage I1.

The signature computation block SIGN_M is described in the FIG. 5. Inthis non-limited embodiment, in order to compute a signature of 60 bits,said computation block SIGN_M comprises:

-   -   a first set of 60 flip-flops FFAi, numbered 0 to 59 (i=0, . . .        59), associated with 60 XOR-gates and 60 AND-gates, a first        multiplexer MUXAi (i=0, . . . 59) being associated with each        first flip flop FFAi,    -   a second set of 60 flip-flops FFBi, numbered 0 to 59 (i=0, . . .        59), a second multiplexer MUXBi (i=0, . . . 59) being associated        with each second flip flop FFBi.    -   Each flip flop FFAi of the first set is clocked by sample clock        VCP via the first clock pin CL, whereas each flip flop FFBi of        the second set is clocked by clock CLK2 of the testing board        AFTE via the second pin clock TCK.    -   As shown in the FIG. 5, the computation block SIGN_M is divided        in 60 sub-blocks SBLi, i=0, . . . , 59, each sub-block        comprising:    -   a first flip flop FFAi with its associated XOR-gate, AND-gate,        and first multiplexer MUXAi, and    -   a second flip-flop FFBi with associated second multiplexer        MUXBi.    -   At a time t, a sub-block computes a result value NEWi that is        the result of a XOR between a data sample Pi and a register        value REGi+1 of the next sub-block SBi+1 that has been computed        the preceding time t−1 and stored in the first flip flop FFAi+1        of the next sub-block SBi+1. Hence, NEWi(t)=Pi(t) XOR REGi+1(t)        [1].

The sub-block SB4 is taken in the example of the FIG. 5.

In practice, a result value is processed as follows.

When the initialization pin INIT is reset, the flag TDI being set to 0,the computation can begin according to the formula [1] described abovefor each sub-block SBi. At each sample clock cycle VCP on the clock pinCL, a new pixel Pi is input in the XOR gate of the correspondingsub-block SBi. Thus, the result value NEWi(t) changes at each clockcycle VCP. Then, at each rising edge of the sample clock VCP, the resultvalue NEWi(t) is stored in the first flip-flop FFAi and will be usedwithin the preceding sub-block Sbi−1 for the next time t+1 as a registervalue REGi. Note that when the initialization pin is set to one, theresult values NEWi are null.

It is to be noted that the last sub-block SB59 does not have anyregister value REG59, and that its result value NEW59 is different fromthe other result values NEWi. Thus,

-   -   REGi(t)=NEWi(t−1)=Pi(t−1) XOR REGi+1(t−1), i=0 to 58 and        REG59(t)=P59(t−1) XOR REG0(t−1) XOR REG57(t−1).

When all the result values NEWi(t) have been computed and stored in thecorresponding first flip-flops FFAi, it means that the signaturecomputation of an image I is over. The end of an image I computation isdefined by the vertical synchronization signal VS as described before.

Then, as described before, the testing board AFTE sets the flag TDI toone and the clock cycles of clock CLK2 begin. At the first clock cycle,the register values REGi of each sub-block SBi are stored in the secondflip flops SBi via the second multiplexers MUXBi control, resulting in astore value Bi. Then at the following clock cycle, the last value B59stored is output on the serial output TDO. Then the next clock cycle,the previous value B58 stored is output on the serial output TDO and soforth until all the register values Bi are output. The signature is thusoutput on the serial output TDO. Thus, it is to be noted that one has 61clock cycles on the clock pin TCK, the first one coming from thevertical synchronization signal VS and the 60 following clock cyclescoming from the testing board AFTE, i.e. from the clock CLK2, as shownon FIG. 3.

Note that when the third clock cycle (i.e. just after there-initialization by the delay line) on the pin TCK is produced, thecomputation of another signature can begin without having values of thepreceding signature being lost because these values have been saved inthe second flip flops FFBi. Thus, the first flip flops FFAi can beinitialized via the initialization pin INIT, which is set to 1 by meansof the delay line 2 clock cycles after VS is asserted. Two flip-flopsare used for the initialization of the initialization pin INIT and theother two for the reset.

It is to be noted that there is a comparison of said second computedsignatures with the registered signatures each time a signature iscomputed as described above. The reference signatures are read by thetesting board AFTE via its universal serial bus USB or universalasynchronous receiver transmitter UART port.

Then the central processing unit CPU2 of the testing board AFTE managesthe results of the comparisons, calculates the rate of return and therate of failures. Preferably, in order to have some good statistics onthese rates, one stores which signatures of which formats are faulty andthe number of time they are faulty.

Note that for the testing board AFTE, no extra pins are added to testthe decoder DEC_V. A testing board AFTE has usually four pins associatedto the four pins TCK, TDO, TDI of the decoder DEC_V.

Note also that the referenced signatures are stored in the read onlymemory ROM of a testing board AFTE, either directly from the referencedcircuit DEC_RF or from an external PC where the referenced signaturescan have been stored. This last solution permits to run a plurality oftesting board AFTE and to avoid inserting each time the referencedcircuit in a testing board.

Thus, according to the invention, as the signatures for the images arecomputed as when the decoder DEC_V is running in its functionalenvironment, that is to say when a video film is being generated by saiddecoder DEC_V said decoder is tested in real time.

Thus, the decoder is tested within its functional environment as if itis running in a customer's environment, such customer being anintegrator that sells consumer equipment such as a set-top-box to abroadcaster for example. The set-top-box is in this case the videoprocessing device and comprises the decoder, a tuner and a LCD screenfor example. Thus, it avoids having too many faulty integrated circuitsreturned by a customer. The functional testing that tests the functions(the decoding function in the example taken) of an integrated circuit isbetter in terms of quality for a customer than the structural testingthat only tests the logic of each component of said integrated circuit.Hence, the customer knows if his whole consumer equipment does not work.Indeed, if its tuner does not work for example, the error will affectthe decoder, which will output a false signature.

Another advantage is that according to the invention, the solutionproposed is not only dedicated to a specific architecture such as aRAMDAC but can be applied on other architecture of integrated circuits.

Furthermore, as the decoder is tested as in its functional environment,it permits to use the usual memory for the decoding application that iswithin the decoder in its usual data bus frequency of 166 MHz or 133MHz, which is impossible for automated test equipment ATE described insome other prior art because such ATE can bear such fast frequencies aswell known by those skilled in the art. Indeed, if the data busfrequency is too high, it leads to too many noise on said bus thatdisrupt the ATE.

Note that the usual memory of a decoder is generally a synchronousdynamic random access memory SDRAM for storing data such as data samplesfor example.

Another advantage is that the testing board for testing the decoder isthe master of the signatures computation. It is totally asynchronous tothe decoder. Indeed, the testing board begins the signature computationwhen ever it wants within the reception of two images (within 20 ms forthe European format 50 Hz, i.e. within the comparison time window)whereas in the prior art described before the signature computationdepends on the frame buffer i.e. random access memory RAM refreshing theintegrated circuit itself and also upon ithe computation speed of itscentral processing unit CPU. Indeed, in the prior art an image is storedin the frame buffer, the central processing unit CPU of the integratedcircuit has to be very fast to compute a signature of an image beforeanother image is stored in the frame buffer and erase the image beingprocessed. If the central processing unit CPU is too slow, the signaturewill be faulty, as it will take some data samples of the next imagealso. In some cases, one can find in the prior art a double frame bufferto solve this problem, but this double frame buffer takes a lot of roomon the silicon of the integrated circuit.

A fifth advantage of the integrated circuit according to the inventionis that the signatures are computed by means of computing means that useonly flip flops. No central processing unit is needed, the consumptionof the decoder is thus decreased in terms of energy. No RAM is used. Itavoids using too much room on the silicon of the decoder.

A sixth advantage is that no extra pins are added to implement theinvention either on the decoder or on the testing board itself. Hencethe invention can be simply implemented on an integrated circuit andtesting board that already exist.

A seventh advantage is that the testing method according to theinvention does not use two integrated circuits in parallel on thetesting board as can be seen in some other prior art. It avoids having aproblem of finding room on the testing board, said testing board beingusually standardized and having usually not too much room. It avoidsalso the problem of synchronizing said two integrated circuits on thetesting board.

An eighth advantage is that the use of signatures instead of the imagesthemselves to test the decoder permits to reduce the memory used for thetesting. Indeed, instead of having a memory or registers of someMegabytes (an image taking about 1 Mbyte), one has a memory or registersof a few bits.

Finally, as all the pixels of an image are taken into account in thesignature computation, the inactive zone within said image is alsotested. Said inactive zone corresponds to the characters usually called“teletext” that appear above a visual image seen by the user of a TV forexample.

It is to be understood that the present invention is not limited to theaforementioned embodiments and variations and modifications may be madewithout departing from the spirit and scope of the invention as definedin the appended claims. In this respect, the following closing remarksare made.

It is to be understood that the present invention is not limited to theaforementioned video application. It can be used in a video encoder forexample.

It can be used within any application using a system with a digitalcircuit. For example it can be used for an integrated circuit used forMPEG compression. In this MPEG application, the counter CT is based on asynchronization pin, a clock pin and a validation pin fortriggering/stopping the beginning of a reading of the signature, forsequencing the reading of the bits of a signature and for validating acompression of an image I respectively. In this case, the signaturecomprises 188 or 204 bytes. The counter CT can be external or internalto the integrated circuit.

Another example can be an integrated circuit for audio application. Inthis case, a data signal is usually called a frame.

It is to be understood that the method according to the presentinvention is not limited to the aforementioned implementation.

There are numerous ways of implementing functions of the methodaccording to the invention by means of items of hardware, provided thata single item of hardware can carry out several functions. It does notexclude that an assembly of items of hardware carry out a function, thusforming a single function without modifying the method of testing anintegrated circuit in accordance with the invention. Said hardware itemscan be implemented in several manners, such as by means of wiredelectronic circuits.

Any reference sign in the following claims should not be construed aslimiting the claim. It will be obvious that the use of the verb “tocomprise” and its conjugations does not exclude the presence of anyother steps or elements besides those defined in any claim. The article“a” or “an” preceding an element or step does not exclude the presenceof a plurality of such elements or steps.

1. An integrated circuit, for processing a plurality of data samples ofa data signal, wherein said integrated circuit is associated with acounter, the integrated circuit comprising: data processing circuitry tocompute a signature, said counter for stopping the data processingcircuitry to trigger recalculating a signature of said data signal, saidsignature to be recalculated each time a data sample of said data signalis output by said integrated circuit, wherein a data signal comprises anactive zone and an inactive zone, which are both taken into account forthe signature computation.
 2. An integrted circuit for processing aplurality of data samples of a data signal, wherein said integratedcircuit is associated with a counter, the integrated circuit comprising:data processing circuitry to compute a signature, said counter forstopping the data processing circuitry to trigger recalculating asignature of said data signal, said signature to be recalculated eachtime a data sample of said data signal is output by said integratedcircuit; and an initialization input for outputting a signal definingthat said integrated circuit is in a test mode or not, a clock pin forreceiving a clock signal of a data testing system, a flag for enablingthe reading of a signature by a data testing system, and a serial outputfor outputting the bits of a signature to said data testing system. 3.An integrated circuit for processing a plurality of data samples of adata signal, wherein said integrated circuit is associated with acounter, the integrated circuit comprising: data processing circuitry tocompute a signature, said counter for stopping the data processingcircuitry to trigger recalculating a signature of said data signal, saidsignature to be recalculated each time a data sample of said data signalis output by said integrated circuit; and a delay line for initializingthe signature computation block.
 4. An integrated circuit, forprocessing a plurality of data samples of a data signal, wherein saidintegrated circuit is associated with a counter, the integrated circuitcomprising: data processing circuitry to compute a signature, saidcounter for stopping the data processing circuitry to triggerrecalculating a signature of said data signal, said signature to berecalculated each time a data sample of said data signal is output bysaid integrated circuit, wherein in real time and synchronous witharrival of a new data sample, the counter stops the data processingcircuitry to trigger recalculating a signature.
 5. A method of testingan integrated circuit for processing a plurality of data samples of adata signal, said integrated circuit being associated to a counter,wherein said method comprises the steps of: inserting said integratedcircuit in a data resting system, computing a signature for all the datasingals generated by said integrated circuit using said counter totrigger and stop a computation of a signature of a signal, saidsignature being recalculated each time a data sample of a data signal isoutput by said integrted circuit, and comparing in real time saidcomputed signatures with some registered signatures of a referencedintegrated circuit each time a signature is computed, a result of thecomparison being used to determine whether of not said integratedcircuit is faulty, wherein computing a signature is performed withoutuse of a CPU amd without use of a buffer to store the data samples.
 6. Amethod of testing an integrated circuit for processing a plurality ofdata samples of a data signal, said integrated circuit being associatedto a counter, wherein said method comprises the steps of: inserting saidintegrated circuit in a data testing system, computing a signature forall the data signals generated by said integrated circuit using saidcounter to trigger and stop a computation of a signature of a signal,said signature being recalculated each time a data sample of a datasignal is output by said integrated circuit, and comparing in real timesaid computed signatures with some registered signatures of a referencedintegrated circuit each time a signature is computed, a result of thecomparison being used to determine whether or not said integratedcircuit is faulty, wherein computing a signature is performed using flipflops.